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CMX644A
V.22 and Bell 212A Modem
D/644A/6 June 2000 Provisional Issue
Features
* * * * * * V.22/Bell 212A Compatible Modem Integrated DTMF Encoder Call Progress/Accurate Answer Tone Detection Line Reversal and Ringing Detector Low Power Operation (2.7V) Fully Integrated UART Functions
Applications
* * * * * * Telephone Telemetry Systems Remote Utility Meter Reading Security Systems/Cash Terminals Industrial Control Systems Pay-Phones Cable TV Set-Top Boxes
1.1
Brief Description
The CMX644A V.22 modem is intended for use in any telephone based information and telemetry system with low power requirements. Using V.22 signalling, fast call set up times and robust error resistant transmission can be implemented by efficient low power circuits. The circuit can operate at 1200b/s full duplex over 2-or 4wire circuits. Control of the device is via a simple high speed serial bus and data may be optionally formatted by the on-chip UART. This allows easy interfacing to a host Controller. The data transmitted and received by the modem is also transferred over the same high speed serial bus. In addition to V.22, support is included to meet the Bell 212A standard. The integrated DTMF encoder can be used as part of the dial out function. All 16 DTMF combinations are available along with a single tone `melody' mode. The answer tone generator/detector and call progress tone detectors included on the CMX644A make the setup of a telephone call a simple matter for the host Controller. In many data collection and telemetry systems low power consumption is important. The CMX644A features a `Zero Power' standby mode. Whilst in standby, the device can still detect a ringing voltage or line voltage reversal. The CMX644A can operate on a supply voltage between 3.0V and 5.5V across the full temperature range of -40C to +85C. A low impedance pull down output is provided for a hook relay. The CMX644A is pin compatible with the CMX624 V23/Bell 202 modem also from CML.
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CONTENTS Section 1.1 1.2 1.3 1.4 1.5 Page Brief Description ..................................................................................1 Block Diagram......................................................................................3 Signal List ............................................................................................4 External Components ..........................................................................6 General Description.............................................................................7 1.5.1 `C-BUS' Interface .....................................................................7 1.5.2 UART .......................................................................................8 1.5.3 Software Description.............................................................10 Application Notes ..............................................................................21 1.6.1 Line Interface.........................................................................21 1.6.2 Ring Detector Interface .........................................................23 1.6.3 Software Protocol for Transmitting PSK Data Bytes...........24 1.6.4 Software Protocol for Receiving PSK Data Bytes ...............25 1.6.5 Handling Underflow and Overflow Conditions....................25 Performance Specification ................................................................27 1.7.1 Electrical Performance..........................................................27 1.7.2 Packaging ..............................................................................32
1.6
1.7
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1.2
Block Diagram
Figure 1 Block Diagram
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1.3
Signal List
CMX644A D2/D5/P4 Pin No. 1 2 Signal Name XTALN XTAL/CLOCK Type O/P I/P The inverted output of the on-chip oscillator. The input to the on-chip oscillator, for external Xtal circuit or clock. The `C-BUS' serial clock input. This clock, produced by the Controller, is used for the transfer timing of commands to and from the device. The `C-BUS' serial data input from the Controller. Data is loaded into this device in 8bit bytes, MSB (B7) first, and LSB (B0) last, synchronised to the SERIAL CLOCK. The `C-BUS' serial data output to the Controller. The transmission of REPLY DATA bytes is synchronised to the SERIAL CLOCK under control of the CSN input. This 3-state output is held at high impedance when not sending data to the Controller. The `C-BUS' data loading control function: this input is provided by the Controller. Data transfer sequences are initiated, completed or aborted by the CSN signal. This output indicates an interrupt condition to the Controller by going to a logic `0'. This is a `wire-ORable' output, enabling the connection of up to 8 peripherals to 1 interrupt port on the Controller. This pin has a low impedance pulldown to logic `0' when active and a high impedance when inactive. An external pull-up resistor is required. The output of the transmit gain control. The output of the line driver amplifier. The inverting input to the line driver amplifier. The inverted output of the line driving amplifier. Pins TXO and TXON provide symmetrical outputs for use with a balanced load to give sufficient Tx line signal levels even at low VDD. Description
3
SERIAL CLOCK
I/P
4
COMMAND DATA
I/P
5
REPLY DATA
T/S
6
CSN
I/P
7
IRQN
O/P
8 9 10 11
TOP TXO TXN TXON
O/P O/P I/P O/P
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1.3
Signal List (Continued)
CMX644A D2/D5/P4 Pin No. 12 13 Signal Name VSS VBIAS Type POWER O/P The negative supply rail (ground). A bias line for the internally circuitry, held at 1/2 VDD. This pin must be decoupled by a capacitor mounted close to the device pins. An open-drain output for controlling a relay. The non-inverting input of the receive op-amp. The inverting input of the receive op-amp. The output of the receive op-amp. Open-drain output and Schmitt trigger input forming part of the Ring or Line Polarity Reversal detector. An external resistor to VDD and a capacitor to VSS should be connected to RT to filter and extend the RD input signal. Input to the Ring or Line Polarity Reversal Detector. No connections should be made to these pins. Description
14 15 16 17 18
RLYDRV RXP RXN RXO RT
O/P I/P I/P O/P BI
19
RD
I/P
20, 21, 22 23
-
N/C
ATODCAP
O/P
The reference voltage for the internal A to D of the receiver. This pin must be decoupled by a capacitor mounted close to the device pins. The positive supply rail. Levels and thresholds within the device are proportional to this voltage. Should be decoupled to VSS by a capacitor mounted close to the device pins.
24
VDD
POWER
Notes: I/P O/P N/C B/I T/S
= = = = =
Input Output No (external) Connections Bidirectional Tristate
This device is capable of detecting and decoding small amplitude signals. It is recommended that the printed circuit board is laid out with a ground plane in the CMX644A area to provide a low impedance connection between the VSS pin and the VDD and VBIAS decoupling capacitors. The receive path should be protected as much as possible from extraneous signals.
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1.4
External Components
R1 X1
100k * 3.6864MHz, 7.372800MHz or 11.0592MHz
C1, C2 C3, C4 C5
18pF 0.1F 1F
Resistors 1%, capacitors 20% unless otherwise stated. * R1 should be selected so that the IRQN pin has returned to its normal (high) state before the CSN pin goes high. Figure 2 Recommended External Components for Typical Application
Notes on Xtal Osc and Clock Dividers Frequency and timing accuracy of the CMX644A is determined by the clock present at the XTAL/CLOCK pin. This may be generated by the on-chip oscillator inverter using the external components C1, C2 and X1 of Figure 2, or may be supplied from an external source to the XTAL/CLOCK input. If the clock is supplied from an external source, C1, C2 and X1 should not be fitted. The on-chip oscillator is turned off in the 'Zero-Power' mode. If the clock is provided by an external source which is not always running, then the 'Zero-Power' mode must be set when the clock is not available. Failure to observe this rule may cause a rise in the supply current drawn by CMX644A.
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1.5
1.5.1
General Description
`C-BUS' Interface
This block provides for the transfer of data and control or status information between the CMX644A's internal registers and the C over the `C-BUS' serial bus. Each transaction, see Figure 3, consists of a single Register Address byte sent from the C which may be followed by a single data byte sent from the C to be written into one of the CMX644A's Write Only Registers, or a single byte of data read out from one of the CMX644A's Read Only Registers. Data sent from the C on the Command Data line is clocked into the CMX644A on the rising edge of the Serial Clock input. Reply Data sent from the CMX644A to the C is valid when the Serial Clock is high. The interface is compatible with the most common C serial interfaces such as SCI, SPI and Microwire, and may also be easily implemented with general purpose C I/O pins controlled by a simple software routine. See section 1.7.1 and Figure 9 for detailed `C-BUS' timing requirements.
Figure 3 `C-BUS' Transactions
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1.5.2
UART
This block connects the C, via the `C-BUS' interface, to the received data from the PSK Demodulator and to the transmit data input to the PSK Modulator. As part of this function, the block can be programmed to convert data to be transmitted from 7 or 8-bit bytes to asynchronous data characters, adding Start and Stop bits and - optionally - a parity bit to the data before passing it to the PSK Modulator. Similarly, in the receive direction it can extract data bits from asynchronous characters coming from the PSK Demodulator, stripping off the Start and Stop bits and performing an optional Parity check on the received data before passing the result over the `C-BUS' to the C. Bits 0-5 of the UART MODE Register control the number of Stop and Data bits and the Parity options for both receive and transmit directions. Data to be transmitted should be loaded by the C into the TX DATA BYTE Register when the Tx Data Ready bit (bit 1) of the FLAGS Register goes high. It will then be treated by the Tx UART block in one of two ways, depending on the setting of bit 5 of the UART MODE Register: If bit 5 of the UART MODE Register is `0' (`Sync' mode) then the 8 bits from the TX DATA BYTE Register will be transmitted sequentially LSB (D0) first. If bit 5 of the UART MODE Register is `1' (`Async' mode) then the 7 or 8 bits will be transmitted as asynchronous data characters according to the following format: One Start bit (Space). 7 or 8 Data bits from the TX DATA BYTE Register (D0-D6 or D0-D7) as determined by bit 0 of the UART MODE Register. LSB (D0) transmitted first. Optional Parity bit (even or odd parity) as determined by bits 1 and 2 of the UART MODE Register. Zero, One or Two Stop bits (Mark) as determined by bits 3 and 4 of the UART MODE Register. In both cases data will only be transmitted if bit 6 of the TX PSK MODE Register is set to `1'. Failure to load the TX DATA BYTE Register with a new value when required will result in bit 2 (TX DATA UNDERFLOW) of the FLAGS Register being set to `1' and a continuous Mark (`1') signal will then be transmitted until a new value is loaded into TX DATA BYTE Register.
Figure 4a Transmit UART Function (Async)
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Received data from the PSK Demodulator goes into the receive part of the UART block, where it is handled in one of two ways depending on the setting of bit 5 of the UART MODE Register: If bit 5 of the UART MODE Register is `0' (`Sync' mode) then the receive part of the UART block will simply take 8 consecutive bits from the Demodulator and transfer them to the RX DATA BYTE Register (the first bit going into the D0 position). If bit 5 of the UART MODE Register is `1' (`Async' mode) then the received data output of the PSK Demodulator is treated as asynchronous characters each comprising: A Start bit (Space). 7 or 8 Data bits as determined by bit 0 of the UART MODE Register. These bits will be placed into the RX DATA BYTE Register with the first bit received going into the D0 position. An optional Parity bit as determined by bits 1 and 2 of the UART MODE Register. If Parity is enabled (bit 2 of the UART MODE Register = `1') then bit 7 of the FLAGS Register will be set to `1' if the received parity is incorrect. Any number of Stop bits (Mark). Bit 3 (RX DATA READY) of the FLAGS Register will be set to `1' every time a new received value is loaded into the RX DATA BYTE Register. If the previous contents of the RX DATA BYTE Register had not been read out over the `C-BUS' before the new value is loaded from the UART then bit 4 (RX DATA OVERFLOW) of the FLAGS Register will also be set to `1'.
Figure 4b Receive UART Function (Async)
The C-BUS serial clock should be fast enough to ensure that an RX DATA READY interrupt is serviced completely within a time which is less than 8 bit-times at 1200 baud, i.e. in less than 6.67ms.
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1.5.3
Software Description
HEX ADDRESS/ COMMAND $01
Write-only `C-BUS' Registers
REGISTER NAME GENERAL RESET BIT 7 (D7) N/A BIT 6 (D6) N/A RELAY DRIVE TONE / NOTONE TXGAIN TG2 BIT 5 (D5) N/A DETECT DET1 DTMF / MODEM TONES TXGAIN TG1 BIT 4 (D4) N/A DETECT DET0 DTMF / SNGL TXGAIN TG0 BIT 3 (D3) N/A LOOPBACK: L1 D3 RXGAIN RG3 BIT 2 (D2) N/A LOOPBACK: L0 D2 RXGAIN RG2 BIT 1 (D1) N/A XTAL FRQ: X1 D1 RXGAIN RG1 BIT 0 (D0) N/A XTAL FRQ: X0 D0 RXGAIN RG0
SET-UP TX TONES GAIN BLOCKS TX DATA BYTE UART MODE TX PSK MODE RX PSK MODE IRQ MASK BITS
$E0
0 TONE SEL TXGAIN TG3
$E1
$E2
$E3 $E4
D7 0
D6 0
D5 SYNC/ ASYNC SCRAMB UNLOCK DESCRAMB UNLOCK DETECT
D4 STOP BITS B SCRAMB ENABLE DESCRAMB ENABLE RX DATA OVERFLOW
D3 STOP BITS A EQUAL ET1 EQUAL ER1 RX DATA READY
D2 PARITY ENABLE EQUAL ET0 EQUAL ER0 TX DATA UNDERFLOW
D1 PARITY ODD/ EVEN ENABLE
D0 DATA BITS 8/7 HI / LO BAND HI / LO BAND UN-SCRAM MARK
$E7
0
TXON ENAB CPBW SELECT RING DETECT
$E8
0 RX PARITY
ENABLE TX DATA READY
$EE
Write-only Register Descriptions GENERAL RESET ($01) The reset command has no data attached to it. Application of the GENERAL RESET sets all write-only register bits to `0'. SET-UP Register ($E0) (Bit 7) RELAY DRIVE (Bit 6) Reserved for future use. This bit should be set to `0'. This bit controls a low impedance pull-down transistor connected to the RLYDRV pin to assist with the operation of an `off-hook relay'. When set to `1' the transistor acts as a pull-down and will sink current. When set to `0' the pin is in a high impedance state. These 2 bits control the operation of the receiver filter in order to facilitate the detection of the following signals as shown in the table below: DET1 Bit 5 DET0 Bit 4 Required Rx HI/LO Band Setting (Register $E8, Bit 0)
DETECT DET1 and DET0 (Bits 5 and 4)
Detection Mode 0 0 As required for Rx PSK PSK Carrier 0 1 LO = `0' Call Progress 1 0 HI = `1' Answer Tone 1 1 As required for Rx PSK Detectors OFF Rx PSK MODE register ENABLE bit should be set to `1' for answertone and call progress detection.
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LOOPBACK L1 and L0 (Bits 3 and 2)
These 2 bits control internal signal paths such that loopback tests can be performed. Function is according to the following table: L1 Bit 3 0 0 L0 Bit 2 0 1
1
0
1 XTAL FRQ X1 and X0 (Bits 1 and 0)
1
Normal Device Operation: no loopback. Local Analogue Loopback: the output of the Tx gain block is routed to the input of the receiver gain block. (The connection between the receiver op-amp and gain block is broken). Local Digital Loopback: data is loaded into the TX DATA BYTE register in the usual way via the `C-BUS' when indicated by the TX DATA READY flag. This digital data is internally retimed serially to the modem bit-rate and is then clocked into the receiver buffer. When the receiver buffer is full the RX DATA READY flag will be set and the data can then be read out of RX DATA BYTE register via the `C-BUS'. Reserved for future use.
These two bits control the internal primary clock dividers to allow for a choice of 3 crystal frequencies. They can also be set to put the device into `Zero Power' mode: in this mode all functions are powersaved, except for the `C-BUS' and the Ring Detector. In `Zero Power' the crystal oscillator is disabled and the Bias resistor chain is disconnected from the supplies. Note: When the device is brought out of `Zero Power' mode, the software should allow at least 20ms for the crystal oscillator to re-start and for the Bias capacitor to re-charge, before proceeding with any further device functions. The function is given by the following table: X1 Bit 1 0 0 1 1 X0 Bit 0 0 1 0 1
Crystal / Mode `Zero Power' 3.6864MHz crystal 7.3728MHz crystal 11.0592MHz crystal
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TX TONES Register ($E1) This register is used to transmit both DTMF and modem progress tones. TONESEL (Bit 7) TONE/NOTONE (Bit 6) This bit selects the "Answer Tone" frequency in the receive detector. A `0' selects 2225Hz and a `1' selects 2100Hz. This bit should be used to begin and end the transmission of tones once the required frequency has been programmed. When set to `1' the tone will be transmitted; when set to `0' a Notone (Bias Voltage) will be generated. When this bit is set to `1' the device is configured for DTMF. When it is set to `0' the device is configured to transmit modem progress tones. For normal DTMF operation this bit should be set to `0'. For test purposes it can be set to `1' in order to select the tone frequencies individually.
DTMF/MODEM TONES (Bit 5) DTMF/SNGL (Bit 4)
The following table shows the settings required for transmitting DTMF (Bit 5 should be set to `1'. Bits 6 and 7 should be operated as described above). Lower Freq. (Hz) (setting Bit 4 = 0) 941 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 Upper Freq. (Hz) (setting Bit 4 = 0) 1633 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 Keypad symbol D 1 2 3 4 5 6 7 8 9 0 * # A B C Single Tone Freq. (Hz) (setting Bit 4 = 1) 1633 1209 1336 1477 1209 1336 1477 1209 852 852 941 941 941 697 770 852
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
The following table shows the settings required for transmitting modem progress tones. (Set Bit 4 to `0' and Bit 5 to `0'. Bits 6 and 7 should be operated as described earlier). D3 0 0 0 0 0 D2 0 0 0 0 1 D1 0 0 1 1 0 D0 0 1 0 1 0 Frequency (Hz) 550 1300 1800 2100 2225 Tone Description Guard Calling Guard Answer Answer
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GAIN BLOCKS Register ($E2) Bits 0 to 3 (RG0 to RG3) control the levels of the receiver input gain block according to the following table: RG3 (Bit 3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RG2 (Bit 2) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RG1 (Bit 1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RG0 (Bit 0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
GAIN (dB) -4.70 -3.46 -2.12 -0.96 0.00 0.87 1.64 2.36 3.08 3.69 4.22 4.76 5.27 5.78 6.21 6.58
The gain should be set in a calibration procedure in order to trim out the effects of any component tolerances which may give rise to a variation in the Carrier Detect Threshold levels. Bits 4 to 7 (TG0 to TG3) control the levels of the transmit path gain block according to the following table: TG3 (Bit 7) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TG2 (Bit 6) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TG1 (Bit 5) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TG0 (Bit 4) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
GAIN (dB) OFF (o/p at Bias) -5.6 -5.2 -4.8 -4.4 -4.0 -3.6 -3.2 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0
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TX DATA BYTE Register ($E3) The bytes of data to be transmitted should be loaded into this register. It is double buffered, thus giving the user up to 8 bit periods to load in the next 8 bits. Each byte represents 4 lots of 2 consecutive bits (dibits) with the most significant dibit being loaded first (taking Bit 7 of this register as being the most significant). The data is reversed so that it is transmitted least significant dibit first. These dibits represent a transmitted phase change according to the following table: Dibit values 00 01 11 10 Phase change + 90 0 + 270 + 180 Note that the left-hand digit of the dibit is the one occurring first in the data stream as it enters the modulator portion of the modem after the scrambler.
UART MODE Register ($E4) (Bit 7 and Bit 6) SYNC/ASYNC (Bit 5) Reserved for future use. These bits should be set to `0'. When this bit is `0', data will be transmitted and received in normal 8 bit mode without modification. When this bit is `1', data will be transmitted and received with one start bit (`0') and 7/8 bits, odd/even parity, 0 or 1 or 2 stop bits according to the remainder of the bits in this register. Prior to handshaking the UART Mode register needs Bit 5 cleared for synchronous operation. After the handshaking procedure has completed Bit 5 the UART Mode register should be set for asynchronous data transfer. The remaining bits of this register should be configured to be compatible with the modem you are talking to. The minimum number of stop bits only applies to the transmitter, the receiver does not require any defined number of stop bits. STOP BITS A and B (Bits 4 and 3) The minimum number of stop bits transmitted after each data byte plus parity is defined by the table below. Stop Bits A 0 0 1 1 Stop Bits B 0 1 0 1 Number of Stop Bits 0 1 1 2
The receiver does not require any defined number of stop bits. PARITY ENABLE (Bit 2) When this bit is `1' an extra bit is added after the data to indicate the parity of that data. When set to `0', parity is disabled. This bit affects both transmitter and receiver. When this bit is `1' the parity is set odd, and when this bit is `0' the parity is set even. This bit affects both transmitter and receiver. When this bit is `1' the data is set to transmit and receive 7 bits i.e. bits 0 - 6. When this bit is `0' the normal 8 bits of data is programmed. This bit affects both transmitter and receiver.
PARITY ODD/EVEN (Bit 1)
DATA BITS 8/7 (Bit 0)
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TX PSK MODE Register ($E7) (Bit 7) TXON ENAB (Bit 6) Reserved for future use. This bit should be set to `0'. This bit enables or powersaves the inverted output of the line driving amplifier (TXON). When set to `1' TXON is enabled; together with TXO these outputs provide sufficient complementary output to drive a line even at low VDD. When set to `0' the TXON output is powersaved, reducing the total supply current for applications in which a single-ended output is sufficient. When this bit is set to `1' the scrambler will check for sequences of 64 consecutive ones at its output (caused by scrambler lockup) and once detected it will invert the next input to the scrambler. When this bit is set to `0' the lock-up prevention is disabled. When this bit is set to `1' the Tx data is passed through the scrambler. When it is set to `0' the scrambler is bypassed. These 2 bits control the level of equalisation applied to the transmitted signal according to the following table: ET1 (Bit 3) 0 0 1 1 ET0 (Bit 2) 0 1 0 1 Transmitter Equalisation no equalisation Low Medium High
SCRAMB UNLOCK (Bit 5)
SCRAMB ENABLE (Bit 4) EQUAL ET1 and ET0 (Bits 3 and 2)
See Figures 5a and 5b for the typical equaliser responses. The equaliser is automatically powersaved when both ET1 and ET0 are set to '0'. ENABLE (Bit 1) When this bit is set to `1' the internal output of the PSK modulator is enabled. When it is set to `0' the internal output of the PSK modulator is set to VBIAS. Associated flags are only set when this bit is `1'. This bit determines whether the transmitted PSK signal should occupy the low channel (900Hz - 1500Hz) or the high channel (2100Hz 2700Hz). When the bit is set to `0' the low channel is selected. When it is set to `1' the high channel is selected.
HI/LO BAND (Bit 0)
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RX PSK MODE Register ($E8) (Bit 7) CPBW SELECT (Bit 6) Reserved for future use. This bit should be set to `0'. When this bit is set to `1' the Call Progress Detector bandwidth is approximately 300Hz - 620Hz. When this bit is set to `0' the Call Progress Detector bandwidth is approximately 400Hz - 620Hz. When this bit is set to `1' the de-scrambler will check for sequences of 64 consecutive ones at its input and once detected it will invert the next output from the de-scrambler. When this bit is set to `0' the all ones detection is disabled - it should be set as such until the handshaking sequence is complete. When this bit is set to `1' the Rx data is passed through the descrambler. When it is set to `0' the de-scrambler is bypassed. These 2 bits control the level of equalisation applied to the received signal according to the following table: ER1 ER0 Receiver (Bit 3) (Bit 2) Equalisation 0 0 no equalisation 0 1 Low 1 0 Medium 1 1 High See Figures 5a and 5b for the typical equaliser responses. The equaliser is automatically powersaved when ET1 and ET0 are set to "no equalisation" (`0', `0'). ENABLE (Bit 1) When this bit is set to `1' the PSK receiver is enabled. When it is set to `0' the receiver is disabled. Associated flags are only set when this bit is `1'. This bit determines whether the received PSK signal should be filtered and derived from the low channel (900Hz - 1500Hz) or the high channel (2100Hz - 2700Hz). When this bit is set to `0' the low channel is selected. When it is set to `1' the high channel is selected.
DE-SCRAMB UNLOCK (Bit 5)
DE-SCRAMB ENABLE (Bit 4) EQUAL ER1 and ER0 (Bits 3 and 2)
HI/LO BAND (Bit 0)
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IRQ MASK BITS ($EE) This register is used to control the interrupts (IRQs) as described below: RX PARITY mask (Bit 7) When this bit is set to `1' it enables an interrupt that occurs when the RX PARITY flag (Bit 7, FLAGS Register, $EF) changes from `0' to `1' i.e. there is an RX PARITY error. When this bit is `0' the interrupt is masked. When this bit is set to `1' it enables an interrupt that occurs when RING DETECT CHANGE flag (Bit 6, FLAGS Register, $EF) changes from `0' to `1'. When this bit is `0' the interrupt is masked. When this bit is set to `1' it enables an interrupt that occurs when DETECT flag (Bit 5, FLAGS Register, $EF) changes from `0' to `1'. When this bit is `0' the interrupt is masked. When this bit is set to `1' it enables an interrupt that occurs when RX DATA OVERFLOW flag (Bit 4, FLAGS Register, $EF) changes from `0' to `1'. When this bit is `0' the interrupt is masked. When this bit is set to `1' it enables an interrupt that occurs when RX DATA READY flag (Bit 3, FLAGS Register, $EF) changes from `0' to `1'. When this bit is `0' the interrupt is masked. When this bit is set to `1' it enables an interrupt that occurs when TX DATA UNDERFLOW flag (Bit 2, FLAGS Register, $EF) changes from `0' to `1'. When this bit is `0' the interrupt is masked. When this bit is set to `1' it enables an interrupt that occurs when TX DATA READY flag (Bit 1, FLAGS Register, $EF) changes from `0' to `1'. When this bit is `0' the interrupt is masked. When this bit is set to `1' it enables an interrupt that occurs when UNSCRAM MARK flag (Bit 0, FLAGS Register, $EF) changes from `0' to `1'. When this bit is `0' the interrupt is masked.
RING DETECT mask (Bit 6)
DETECT mask (Bit 5)
RX DATA OVERFLOW mask (Bit 4) RX DATA READY mask (Bit 3)
TX DATA UNDERFLOW mask (Bit 2)
TX DATA READY mask (Bit 1) UNSCRAM MARK mask (Bit 0)
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CMX644A
Read Only `C-BUS' Registers
REGISTER NAME RX DATA BYTE TONES DETECT HEX ADDRESS/ COMMAND $EA $EC BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) BIT 4 (D4) BIT 3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0)
D7 1
D6 RING DETECT RING DETECT CHANGE
D5 CALL PRGRSS DETECT DETECT
D4 CARRIER DETECT RX DATA OVERFLOW
D3 ANSWER DETECT RX DATA READY
D2 0
D1 0
FLAGS
$EF
RX PARITY
TX DATA UNDERFLOW
TX DATA READY
D0 UNSCRAM MARK DETECT UNSCRAM MARK
RX DATA BYTE Register ($EA) This register contains the last byte of data received. It is updated every 8 bits at the same time as the RX DATA READY flag is set. The RX DATA BYTE register is double buffered, thus giving the user up to 8 bit periods to read the data before it is overwritten by the next byte. Each received phase change is decoded into 2 bits (a dibit). The incoming dibits fill this register starting at the most significant end (Bits 7 and 6). Phase change + 90 0 + 270 + 180 Dibit values 00 01 11 10 Note that the left-hand digit of the dibit will be the more significant of the 2 bits when located in this register.
TONES DETECT Register ($EC) This register provides information as to the presence or absence of various signalling conditions detected by the receiver. A logic `1' indicates that the signalling condition is present; a logic `0' indicates that it is absent. (Bit 7) RING DETECT (Bit 6) This bit will be set to `1'. Indicates the status of the Ring/Line Polarity Reversal Detector circuit. The logic level of this bit represents the level of the internal `RING DETECT' node (see Figure 1 Block Diagram). Indicates the detection of call progress tones in the selected band. (300Hz to 620Hz or 400Hz to 620Hz). Indicates the detection of a carrier in the received channel.
CALL PRGRSS DETECT (Bit 5) CARRIER DETECT (Bit 4) ANSWER DETECT (Bit 3) (Bits 2 and 1) UNSCRAM MARK DETECT (Bit 0)
Indicates the detection of an Answer Tone of 2100Hz or 2225Hz.
These bits will be set to `0'. Indicates the detection of unscrambled binary one in the received data for a period of time of 160ms.
Note that DETECT bits 5, 4 and 3 are mutually exclusive and are enabled by the setting of the DETECT DET1 and DET0 bits (SET-UP Registers Bits 5 and 4). All of the DETECT bits in the TONES DETECT register - except for RING DETECT (Bit 6) - require the RX PSK MODE register ENABLE bit to be set to `1'. FLAGS Register ($EF) The flags register is used to indicate when the device requires attention. When a flag becomes set to `1' and its corresponding mask bit is `1' then an interrupt (IRQN) will be generated. Immediately after the flags register has been read, all the bits will be reset to `0' and consequently any interrupt will be cleared.
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RX PARITY flag (Bit 7) RING DETECT CHANGE flag (Bit 6) DETECT flag (Bit 5)
When this bit is `1' the received parity is in error. When this bit is `0' the received parity is correct. When RING DETECT (TONES DETECT Register, Bit 6) changes state, this bit will be set to `1'. When any of the following bits - CALL PRGRSS DETECT, CARRIER DETECT or ANSWER DETECT (TONES DETECT Register Bits 5, 4, 3) - change state, this bit will be set to `1'. If received data is not read out of the device within the 8-bit window of RX DATA READY going high, then this bit will be set to `1' to indicate an error condition. When a full byte of data is received and is available in the RX DATA BYTE register, this bit will be set to `1'. There is then an 8-bit window during which the RX DATA BYTE register must be read. If data is not loaded into the TX DATA BYTE register within the 8-bit window of TX DATA READY going high, then this bit will be set to `1' to indicate an error condition. When the Tx data buffer is ready to receive a new byte of data, this bit will be set to `1'. There is then an 8-bit window for the loading of the TX DATA BYTE register. When the UNSCRAM MARK DETECT bit (TONES DETECT Register Bit 0) changes state, this bit will be set to `1'.
RX DATA OVERFLOW flag (Bit 4)
RX DATA READY flag (Bit 3)
TX DATA UNDERFLOW flag (Bit 2)
TX DATA READY flag (Bit 1)
UNSCRAM MARK flag (Bit 0)
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2.0E-03 1.9E-03 1.8E-03 1.7E-03 1.6E-03 1.5E-03 1.4E-03
High
Group delay (secs)
1.3E-03 1.2E-03 1.1E-03 1.0E-03 9.0E-04 8.0E-04 7.0E-04 6.0E-04 5.0E-04 4.0E-04 3.0E-04 2.0E-04 1.0E-04 0.0E+00 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800
Medium
Low
Lowband
Frequency (Hz)
Figure 5a Transmit/Receive Equaliser Responses: Lowband
2.0E-03 1.9E-03 1.8E-03 1.7E-03 1.6E-03 1.5E-03 1.4E-03
High
Group delay (secs)
1.3E-03 1.2E-03 1.1E-03 1.0E-03 9.0E-04 8.0E-04 7.0E-04 6.0E-04 5.0E-04 4.0E-04 3.0E-04 2.0E-04 1.0E-04 0.0E+00 1800
Medium
Low
Highband
1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
Frequency (Hz)
Figure 5b Transmit/Receive Equaliser Responses: Highband The CMX644A utilises two internal equalisers - one is configured for the High Band, the other for the Low Band. The Transmit and Receive paths will be internally switched through the equaliser appropriate to their HI/LO BAND settings. In the event of both Transmit and Receive paths being set to the same band, both equalisers will be bypassed.
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1.6
1.6.1
Application Notes
Line Interface
A line interface circuit is needed to provide dc isolation between the modem and the line, to perform line impedance termination, and to set the correct transmit and receive signal levels. 4-Wire Line Interface Figure 6a shows an interface circuit for use with a 600 4-wire line. The line terminations are provided by R10 and R15, while R11 and R13 should be selected to give the desired transmit and receive levels. When VDD = 5.0V, the gain of the receive input amplifier (R12/R11) should be 6dB (times 2.0) plus whatever additional gain is required to compensate for the loss of the input transformer. At other values of VDD the amplifier gain should be multiplied by the ratio VDD/ 5.0. Thus for R12 = 100k: R11 = 100k (5.0/VDD) / (Input transformer loss * 2.0) where the `Input transformer loss' = (Rx level on 4-wire line) / (level at point A of Figure 6a). Assuming a transformer loss of about 1dB, R11 should be 47k at VDD = 5.0V, and 68k at 3.3V. The value of the resistor R11 is optimised for the carrier detect level. Increasing the input gain (by reducing the value of R11) will improve modem sensitivity.
Note Relay circuit, ac and dc loads and line protection are not shown for clarity. R10 R11 R12 R13 600 See text 100k See text R14 R15 100k 600 C10 C11 C12 C13 100nF 330pF 330pF 100nF
Resistors 1%, capacitors 20%. Figure 6a 4-Wire Line Interface Circuit
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In the transmit direction, the level on the 4-wire line is determined by the level at the TOP pin, the gain of the Output Buffer Amplifier, a loss of nominally 6dB due to the line termination resistor R15, and the loss in the transformer. The TOP pin signal level is proportional to VDD and is also affected by the setting of the transmitter programmable gain block. Assuming that the Tx programmable gain block is set to -2dB (giving a PSK signal level of -4dB wrt 775mVrms at the TOP pin when VDD = 5.0V) and that there is 1dB loss in the transformer, then: Tx PSK 4-wire line level = -(4 +6 +1) + 20 LOG10(2 R14/R13) + 20 LOG10(VDD / 5.0) dBm For example, to generate a nominal Tx FSK line level of -10dBm, R13 should be 180k when VDD = 5.0V, falling to 120k at 3.3V. 2-Wire Line Interface Figure 6b shows an interface circuit suitable for connection to a 600 2-wire line. The circuit also shows how a relay may be driven from the RLYDRV pin. Note that when the CMX644A is powered from less than 5.0V, buffer circuitry will be required to drive a 5V relay.
Note: ac and dc loads and line protection are not shown for clarity R11 R12 R13 R14 See text 100k See text 100k R15 R16 R17 600 120k 100k C11 C12 C13 C14 330pF 330pF 10nF 100nF
Resistors 1%, capacitors 20% Figure 6b 2-Wire Line Interface Circuit This circuit includes a 2-wire to 4-wire hybrid circuit, formed by R11, R15, R16, R17, C13 and the impedance of the line itself, which ensures that the modem receive input and transmit output paths are both coupled efficiently to the line, while minimising coupling from the modem's transmit signal into the receive input. The values of R11 and R13 should be calculated in the same way as for the 4-wire interface circuit of Figure 6a. Note that the component values R17 and C13 depend on the transformer characteristics and should be adjusted to achieve a flat frequency response measured at the RXO pin.
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1.6.2
Ring Detector Interface
Figure 7 shows how the CMX644A may be used to detect the large amplitude Ringing signal received at the start of an incoming telephone call. The ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in series with one of the telephone wires and will pass through either C20 and R20 or C21 and R21 to appear at the top end of R22 (point X in Figure 7) in a rectified and attenuated form. The signal at point X is further attenuated by the potential divider formed by R22 and R23 before being applied to the CMX644A RD input. If the amplitude of the signal appearing at RD is greater than the input threshold (Vthi) of Schmitt trigger 'A' then the N transistor connected to RT will be turned on, pulling the voltage at RT to VSS by discharging the external capacitor C22. The output of the Schmitt trigger 'B' will then go high, setting bit 6 (RING DETECT) of the TONES DETECT register. The minimum amplitude ringing signal that is certain to be detected is ( 0.7 + Vthi [R20 + R22 + R23] / R23 ) 0.707 Vrms where Vthi is the high-going threshold voltage of the Schmitt trigger A With R20 - 22 all 470k as Figure 7, then setting R23 to 68k will guarantee detection of ringing signals of 40Vrms and above for VDD over the range 3.0 to 5.5V.
R20,21,22 R23 R24
470k See text 470k
C20,21 C22 D1 - 4
0.1F 0.33F 1N4004
Resistors 1%, capacitors 20% Figure 7 Ring Signal Detector Interface Circuit
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If the time constant of R24 and C22 is large enough then the voltage on RT will remain below the threshold of the 'B' Schmitt trigger for the duration of a ring cycle. The time for the voltage on RT to charge from VSS towards VDD can be derived from the formula VRT = VDD [1 - exp(-t/(R24 x C22)) ] As the Schmitt trigger high-going input threshold voltage (Vthi) has a minimum value of 0.56 x VDD, then the Schmitt trigger B output will remain high for a time of at least 0.821 x R24 x C22 following a pulse at RD. The values of R24 and C22 given in Figure 7 (470k and 0.33F) give a minimum RT charge time of 100 msec, which is adequate for ring frequencies of 10Hz or above. Note that the circuit will also respond to a telephone line voltage reversal. If necessary the C can distinguish between a Ring signal and a line voltage reversal by measuring the time that bit 6 of the TONES DETECT register (RING DETECT) is high. 1.6.3 Software Protocol for Transmitting PSK Data Bytes
In order to transmit PSK data, the following steps should be followed. For clarity, not all bit settings are described here (but HI/LO Band, Equalisation, Guard Tones, Number of Stop Bits etc. should be set as appropriate). 1. Program SETUP register for correct crystal frequency. Wait at least 20ms if device was previously in `Zero Power' mode before proceeding. Set Tx Gain Block (GAIN BLOCKS Register $E2) to required gain. Set UART mode. Load first data byte into TX DATA BYTE Register ($E3). Read FLAGS Register ($EF) in order to clear it. Set IRQ MASK BITS Register ($EE Bits 2 and 1) to allow appropriate interrupts (TX DATA UNDERFLOW and TX DATA READY). Note: If an underflow occurs, continuous mark (`1') will be transmitted. Set ENABLE bit (TX PSK MODE Register $E7) to `1'. The first byte of data will now be transmitted by the device. Wait for a TX DATA READY generated interrupt (read FLAGS to check and clear the IRQ). Load next TX DATA BYTE. Go to 7.
2. 3. 4. 5.
6.
7. 8. 9.
Note that the transmission should be terminated by setting the ENABLE bit (TX PSK MODE Register) to `0'.
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1.6.4
Software Protocol for Receiving PSK Data Bytes
1. With the device out of `Zero Power' mode, set up all receiver-related functions: Gain, HI/LO Band, Equalisation, UART mode, etc. 2. Perform a dummy read of the Rx DATA BYTE Register ($EA) and discard the result. 3. Read FLAGS Register ($EF) in order to clear it. 4. Set IRQ MASK BITS Register ($EE Bits 7, 4 and 3) to allow appropriate interrupts (RX PARITY, RX DATA OVERFLOW and RX DATA READY). 5. Set ENABLE bit (RX PSK MODE Register $E8) to `1'. 6. Wait for an RX DATA READY generated interrupt (read FLAGS to check and clear the IRQ). 7. Read RX DATA BYTE ($EA). 8. Go to 5. 1.6.5 Handling Underflow and Overflow Conditions
If the RX DATA BYTE Register has not been read before the next byte of Rx data is received, then the RX DATA OVERFLOW flag will be set and the RX DATA BYTE Register will hold the most recent byte of received data. The RX DATA READY flag will remain set if the FLAGS Register is not read before the overflow condition occurrs. Both RX DATA READY and RX DATA OVERFLOW flags are reset upon reading the FLAGS Register, and are not set again until after the RX DATA BYTE Register has been read (ie the overflow condition has been cleared). If the TX DATA BYTE Register is not written to before the last byte of Tx data is sent, then the TX DATA UNDERFLOW flag will be set and the Tx data will then consist of continuous mark ("1"), which will normally be scrambled, until new data is loaded into the TX DATA BYTE Register. The TX DATA READY flag will remain set if the FLAGS Register is not read before the underflow condition occurrs. Both TX DATA READY and TX DATA UNDERFLOW flags are reset upon reading the FLAGS Register, and are not set again until after the TX DATA BYTE Register has been loaded with new data (ie the underflow condition has been cleared). C-BUS transactions to handle underflow and overflow conditions are shown in the timing daigram of Figure 8. Note that allowance should be made for C-BUS latency (TDEL and TLOAD) when changing register settings. eg To change the number of Tx stop bits transmitted with all subsequent data (STOP BITS A and B), first wait until the TX DATA READY flag is set. If this check is not made, then the number of stop bits in the Tx data byte which is currently being sent will be changed.
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Figure 8 ASYNC MODE (Rx and Tx)
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1.7
1.7.1
Performance Specification
Electrical Performance
1.7.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -50 0 -20 Max. 7.0 VDD + 0.3 +50 +50 +20 Units V V mA mA mA
Supply (VDD - VSS) Voltage on any pin to VSS Current into or out of VDD and VSS pins Current sink into RLYDRV pin Current into or out of any other pin
D2 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature D5 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature P4 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
Min. -55 -40 Min. -55 -40 Min. -55 -40
Max. 800 13 +125 +85 Max. 550 9 +125 +85 Max. 800 13 +125 +85
Units mW mW/C C C Units mW mW/C C C Units mW mW/C C C
1.7.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Nominal Xtal frequencies are 3.6864MHz, 7.372800MHz, 11.0592MHz. Min 2.7 -40 -100 Max. 5.5 +85 +100 Units V C ppm
Supply (VDD - VSS) Operating Temperature Xtal Frequency
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1.7.1.3 Operating Characteristics For the following conditions unless otherwise specified: VDD = 2.7V at Tamb = 25C and VDD = 3.0V to 5.5V at Tamb = -40 to +85C. 0dBm corresponds to 775mVrms. Notes DC Parameters IDD (`Zero Power') IDD (Operating at VDD = 3.0V and Tamb = 25C) IDD (as above, but with equalisation enabled) Logic `1' Input Level Logic `0' Input Level Logic Input Leakage Current (Vin = 0 to VDD), (excluding XTAL/CLOCK input) Output Logic `1' Level (IOH = 360A) Output Logic `0' Level (IOL = 360A) IRQN O/P `Off' State Current (Vout = VDD) Schmitt trigger input high-going threshold (Vthi) (see Figure 8) Schmitt trigger input low-going threshold (Vtlo) (See Figure 8) Relay Driver pull-down on resistance (VDD = 5.0V, 50mA maximum load current) Xtal/Clock Input Pulse Width (`High' or `Low') Input impedance (at 100Hz) Gain (I/P = 1mV rms at 1kHz) AC Parameters Transmitter (at TOP pin) Guard Tones Level (below PSK) of 550Hz Level (below PSK) of 1800Hz Frequency Accuracy PSK Output Transmitted level Distortion DTMF Output Transmitted level: high group Twist (high group - low group levels) Distortion Frequency Accuracy 1, 4,8 -0.25 -3.0 -2.0 -0.25 -3.0 -6.0 -2.0 2.0 -1.0 2.0 2.0 +0.25 -1.0 5.0 0 5 +0.25 dB dB % dBm % dBm dB % % 2 2 2 5 5 Min. 70% -1.0 VDD -0.4 0.56VDD Typ. 1 3.2 Max. 4.0 4.6 30% +1.0 Units A mA mA VDD VDD A
V 0.4 V 1.0 A 0.56VDD+0.6V V 0.44VDD V
0.44VDD -0.6V 37.0
3
40 10 20
-
-
ns M dB
1, 4 4
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Notes Receiver Dynamic Range (VDD = 5.0V) Carrier Detect Threshold: Will Decode Threshold: Will Not Decode Hysteresis Response Time (Delay) De-Response Time (Hold) Answer Tone Detector Threshold: Will Decode Threshold: Will Not Decode Response Time (Delay) De-Response Time (Hold) Decode Bandwidth (must decode) Decode Bandwidth (must not decode) Call Progress Detector Effective Bandwidth Threshold: Will Decode Threshold: Will Not Decode Response Time (Delay) De-Response Time (Hold) Programmable Gain Blocks Rx Gain Block Nominal Range (Step Size: see Register Description) Step Accuracy Tx Gain Block Nominal Range Step Size Step Accuracy Notes: 1. 2. 3. 4. 5. 6. 1, 6 1, 6 7
Min. -48 -48 2.0 300/400 -48 -
Typ. 45 2.0 20 20 20 20 20 20
Max. -43 50 50 -43 50 50 6.0 620 -43 50 50
Units dB dBm dBm dB ms ms dBm dBm ms ms % % Hz dBm dBm ms ms
1, 6 1, 6
9 1, 6 1, 6
-4.70 -0.5 -5.6 -0.2
0.4 -
+6.58 +0.5 0.0 +0.2
dB dB dB dB dB
7.
8. 9. 10.
At VDD = 5.0V only. Signal levels or currents are proportional to VDD. Not including any current drawn from the modem pins by external circuitry. Timing for an external input to the CLOCK/XTAL pin. Tx Gain Block set to 0dB and measured with a pure tone or DTMF tone pair, without equalisation. Excluding RD, RT and XTAL/CLOCK pins. Rx Gain Block nominally set to 0dB but adjusted if necessary for component tolerances. Measurement point for threshold levels is prior to receive input amplifier circuit (point A on Figure 6a), with external components setting gain to 9dB. Detector levels measured with a pure tone. Hysteresis may be increased, if required, by adding one step (increasing the gain of) to the Rx Gain Block when a signal is detected and by removing this step when the signal is no longer detected. Measured with a 511-bit pseudorandom sequence. Depending on the setting of the CPBW SELECT bit in the RX PSK MODE Register. Measured without equalisation.
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3.5 3 2.5 2 V in 1.5 1 0.5 0 2.5 3 3.5 4 Vdd 4.5 5 5.5 V thi V tlo
Figure 9 Typical Schmitt Trigger Input Voltage vs. VDD
Tx Timings (See Figure 4a) Tx Delay from Tx data loaded (TDEL) Tx Output to Tx reload signal (TLOAD) Tx Parity to Tx Underflow flag set (TUFL) Rx Timings (See Figure 4b) Parity to Rx Data Ready flag set (TRDY)
Notes 10
Min. 0
Typ. -
Max. 0.833
Units ms
10
0
-
8.33
ms
ms 10 Notes 10 0 Min. Typ. 1.667 1.667 Max. Units ms
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1.7.1.3 Operating Characteristics (continued) `C-BUS' Timings (See Figure 10) tCSE tCSH tLOZ tHIZ tCSOFF tNXT tCK tCH tCL tCDS tCDH tRDS tRDH Note: CSN-Enable to Clock-High time Last Clock-High to CSN-High time Clock-Low to Reply Output enable time CSN-High to Reply Output 3-state time CSN-High Time between transactions Inter-Byte time Clock-Cycle time Serial Clock-High time Serial Clock-Low time Command Data Set-Up time Command Data Hold time Reply Data Set-Up time Reply Data Hold time Notes Min. 100 100 0 1.0 200 200 100 100 75 25 75 0 Typ. Max. 1.0 Units ns ns ns s s ns ns ns ns ns ns ns ns
These timings are for the latest version of the `C-BUS' as embodied in the CMX644A, and allow faster transfers than the original `C-BUS' timings given in CML Publication D/800/Sys/3 July 1994.
Figure 10 `C-BUS' Timing
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1.7.2
Packaging
Figure 11a 24-pin SOIC (D2) Mechanical Outline: Order as part no. CMX644AD2
Figure 11b 24-pin SSOP (D5) Mechanical Outline: Order as part no. CMX644AD5
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Figure 11c 24-pin DIL (P4) Mechanical Outline: Order as part no. CMX644AP4
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
Oval Park - LANGFORD MALDON - ESSEX CM9 6WG - ENGLAND
Telephone: +44 (0)1621 875500 Telefax: +44 (0)1621 875600 e-mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/1 February 2002

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